Clocking IP for TSMC

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Compare 1,295 Clocking IP for TSMC from 31 vendors (1 - 10)
  • Ultra low-power crystal-based 32 kHz oscillator in TSMC 12FFC+
    • OSC-XT-32k-T12FFC.01_TSMC_12_FFC+ is an ultra-low power crystal-based oscillator in TSMC 12FFC+ for accurate 32 kHz clock generation in the SoC Always-On domain (eg. implementation of RTC features).
    • An embedded auxiliary loop controls the voltage amplitude at the crystal terminals for maximizing the power efficiency for multiple crystals.
    Block Diagram -- Ultra low-power crystal-based 32 kHz oscillator in TSMC 12FFC+
  • Low-power 32 kHz RC low-drift oscillator in TSMC 22ULL
    • OSC-RC-32k-LD-A01-T22ULL.01_TSMC_22_ULL is a 32 kHz RC oscillator in TSMC 22ULL specifically designed for the implemenation of accurate time-based features in always-on domains.
    • With an overall precision better than 500 ppm on its full voltage and temperature operating ranges, Dolphin's IP meets the sleep clock accuracy requirements of the BLE standard, removing the need for an external crystal.
    Block Diagram -- Low-power 32 kHz RC low-drift oscillator in TSMC 22ULL
  • Low-power 32 kHz RC oscillator in TSMC 22ULL 1.8 V
    • OSC-RC-32k-A01-D18-T22ULL.03_TSMC_22_uLL1.8 is a 32 kHz RC oscillator in TSMC 22ULL with 1.8 V I/O MOSFET devices based on a low-power architecture for the implementation of always-on domains.
    • The IP informs the host when the frequency has reached a stable frequency value after leaving shutdown or standby mode.
    Block Diagram -- Low-power 32 kHz RC oscillator in TSMC 22ULL 1.8 V
  • 25MHz to 4.0GHz Fractional-N RC PLL Synthesizer on TSMC 3nm N3P
    • Fractional-N Phase locked loop frequency synthesizer is intended for ASIC clock generation.
    • The Fractional-N PLL loop with 2GHz-4GHz VCO has high phase noise performance and ultra-fine frequency tuning step.
    • VCO Sub-band auto select (SAS) system allows to find automatically appropriate sub-band for VCO on locked PLL.
    Block Diagram -- 25MHz to 4.0GHz Fractional-N RC PLL Synthesizer on TSMC 3nm N3P
  • All Digital Fractional-N RF Frequency Synthesizer PLL in TSMC N6/N7
    • Fractional Multiplication with frequencies up to 8GHz
    • Extremely low jitter (sub 300fs RMS)
    • Small size  (< 0.05 sq mm)
    • Low Power (< 7mW)
    Block Diagram -- All Digital Fractional-N RF Frequency Synthesizer PLL in TSMC N6/N7
  • All Digital Fractional-N PLL for Performance Computing in TSMC N6/N7
    • Fractional multiplication with frequency up to 4GHz
    • Low jitter (< 10ps RMS)
    • Small size  (< 0.01 sq mm)
    • Low Power (< 5mW)
    • Support for multi-PLL systems
    Block Diagram -- All Digital Fractional-N PLL for Performance Computing in TSMC N6/N7
  • Low Power All Digital Fractional-N PLL in TSMC N6/N7
    • Low power, suitable for IoT applications
    • Good jitter, suitable for clocking digital logic.
    • Extremely small die area (< 0.005 sq mm), using a ring oscillator
    • Output frequency can be from 1 to 400 times the input reference, up to 1.5GHz
    Block Diagram -- Low Power All Digital Fractional-N PLL in TSMC N6/N7
  • Low Power All Digital Fractional-N PLL in Samsung 8LPP
    • Low power, suitable for IoT applications
    • Good jitter, suitable for clocking digital logic.
    • Extremely small die area (< 0.005 sq mm), using a ring oscillator
    • Output frequency can be from 1 to 400 times the input reference, up to 1.5GHz
    Block Diagram -- Low Power All Digital Fractional-N PLL in Samsung 8LPP
  • High Speed 16GHz PLL
    • Type II ,3rd order low jitter PLL
    • Auto calibration for process and temperature (USP)
    • Programmable frequency using CSR registers
    • 8/10/16GHz quadrature clocks
    • Operating temperature -40 to 125
    Block Diagram -- High Speed 16GHz PLL
  • Crystal Oscillators
    • The crystal oscillator macros are available in a wide range of industry-standard quartz crystals and MEMS resonators operating in the fundamental mode in the 32 kHz to 80 MHz range.
    • These oscillators, which are both power and area efficient, have a programmable transconductance to allow users to find the optimal balance between jitter and power consumption.
    Block Diagram -- Crystal Oscillators
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