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Clocking IP for TSMC

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Compare 1,310 Clocking IP for TSMC from 32 vendors (1 - 10)
  • High Speed 16GHz PLL
    • Type II ,3rd order low jitter PLL
    • Auto calibration for process and temperature (USP)
    • Programmable frequency using CSR registers
    • 8/10/16GHz quadrature clocks
    • Operating temperature -40 to 125
    Block Diagram -- High Speed 16GHz PLL
  • Crystal Oscillators
    • The crystal oscillator macros are available in a wide range of industry-standard quartz crystals and MEMS resonators operating in the fundamental mode in the 32 kHz to 80 MHz range.
    • These oscillators, which are both power and area efficient, have a programmable transconductance to allow users to find the optimal balance between jitter and power consumption.
    Block Diagram -- Crystal Oscillators
  • Free running oscillators
    • Compact and low power
    • No external components
    • Baseline CMOS logic process masks only
    • Excellent frequency precision over PVT after trimming
    Block Diagram -- Free running oscillators
  • Core Powered Wide Range Programmable Integer PLL on TSMC CLN2P
    • Electrically Programmable PLL with Fractional-N divide and Spread Spectrum Clock Generation
    • Entirely core voltage powered, needs no analog supply voltage
    • Wide Ranges of Input and Output Frequency for diverse clocking needs
    • Very fine precision: near 1 part per billion resolution
    Block Diagram -- Core Powered Wide Range Programmable Integer PLL on TSMC CLN2P
  • 18-40MHz Crystal Oscillator on TSMC CLN2P
    • Crystal Oscillator pad macro that supports industry standard crystals
    • Uses standard CMOS transistors
    • Crystal Oscillation Mode: Fundamental
    • Power down option for IDDQ testing
    Block Diagram -- 18-40MHz Crystal Oscillator on TSMC CLN2P
  • Low Power PLL for TSMC 40nm ULP
    • Wide range M, P, and N integer dividers.
    • 40MHz – 600MHz output frequency range.
    • Input frequency range 1.4MHz – 32MHz.
    • 18pS RMS cycle to cycle jitter.
    • Lock-detect function.
    • Optional bypass function.
    Block Diagram -- Low Power PLL for TSMC 40nm ULP
  • General Purpose PLL for TSMC 152nm
    • Wide range M integer divider. (See ot3122 for M, N, and P dividers)
    • 40MHz – 800MHz output frequency range.
    • Comparable frequency range 8MHz – 32MHz.
    • Optional prescaler.
    • 19pS RMS cycle to cycle jitter at 800MHz.
    • Lock-detect function.
    • Bypass function.
    • 20µS well defined fast startup behavior.
    Block Diagram -- General Purpose PLL for TSMC 152nm
  • PLL for TSMC 130nm LP
    • Wide range N, M, P integer dividers.
    • 40MHz – 600MHz output frequency range.
    • Comparable frequency range 8MHz – 50MHz.
    • 18pS RMS cycle to cycle jitter at 400MHz.
    • Lock-detect function.
    • Bypass function.
    • Well defined startup behavior.
    • -40°C to 125°C temperature operation.
    • Small cell area: 0.022mm2 in 0.13µ CMOS.
    Block Diagram -- PLL for TSMC 130nm LP
  • 5MHz-35MHz Low Power Crystal Oscillator - TSMC 0.18µ
    • 4MHz-35MHz Frequency range.
    • No external bias or limit resistors required.
    • Current optimization for best power at frequency.
    • Amplitude control loop.
    • The OSCI pad input can be used as a CMOS input for test.
    • Uses single 1.8V supply.
    • Enable/power down provision.
    Block Diagram -- 5MHz-35MHz Low Power Crystal Oscillator - TSMC 0.18µ
  • Xtal Oscillator on TSMC CLN7FF
    • Crystal Oscillator pad macro that supports industry standard crystals
    • Uses standard CMOS transistors
    • Crystal Oscillation Mode: Fundamental
    • Power down option for IDDQ testing
    Block Diagram -- Xtal Oscillator on TSMC CLN7FF
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