ADC / DAC IP for Tower
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ADC / DAC IP
for Tower
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Super Inductor IP
- High Inductor Q (10 to 50)
- High Inductor Bandwidth (2.5Ghz to 50Ghz)
- Stackable Design
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Low-Power 8-bit SAR ADC - 8 bits, 50kSPS, Low Voltage (1.8V), Low Power (20µA) TowerJazz 0.18 um
- This macro-cell is a low power, general purpose, 8-bit, 50kSPS, Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) core designed for TowerJazz 0.18μm TS18SL CMOS technology.
- The circuit has an internal sample-and-hold circuit and a power-down operation mode to save power in applications where power consumption is critical.
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10-bit Pipeline ADC - TowerJazz 180 nm
- The A10B25M is an ultra low-power, high-performance analog to digital converter (ADC) intellectual property (IP) design block.
- It is a pipeline ADC that has 10-bit resolution and a sampling rate of up to 25 megasamples per second (MSPS).
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10-Bit Current steering DAC - TowerJazz 0.18um
- Area: 0.088mm2
- Fsmax (Maximum sampling frequency): 16MS/s
- Idd (Current consumption): 3mA
- Resolution (Input digital data resolution): 10bits
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4-bit Flash A/D converter
- 200MSPS
- Hard IP
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13 bits 2.56MS/s SAR ADC - TowerJazz 0.18um
- Area: 0.178mm2
- Fsmax (Maximum sampling frequency): 2.56MS/s
- Idd (Current consumption): 2mA
- Resolution (Output digital data resolution): 13bits