Power Management IP for SMIC

Compare 101 Power Management IP for SMIC from 11 vendors (1 - 10)

Linear Regulator, Low Noise optimized for sensitive application such as RF or PLL blocks
- Low noise: high power Supply Rejection Ratio (PSRR): - 65 dB at F < 10 kHz
- Low intrinsic noise: 20 uVRMS at 10 Hz to 20 kHz
- Low Bill-of-Material: optimized in density for the best trade-off for the given output current and input voltage range
- Cost efficient solution compared to external Power Management.
1.19 V Reference voltage source
- SMIC CMOS 0.18 um
- Output voltage 1.2 V
- Temperature-compensated voltage in a wide temperature range
- Low current consumption
Linear Battery Charger
- CC/CV charge
- Trickle charge when battery voltage is low
- Adjustable charging current with temperature compensation
- Highly accurate end-of-charge voltage
- Load short protection
Ultra low power LDO
- 500mA maximum output current
- Ultra low quiescent current
- low dropout voltage
- Current limit protection
- OTP/OVP/UVP/PGOOD
Ultra low power DCDC
- PWM mode and PSM mode control
- 2A maximum output current
- Dynamic output voltage scaling
- Spread-spectrum frequency modulation
Power On Reset
- Input threshold 2VT.
- Reset and reset bar output logic levels.
- Minimum 8uS reset pulse for any power rise time.
- 1µA typical supply current.
- -40°C to 120°C temperature operation.
75mA Core Voltage Regulator
- Input voltage range 3.0V – 3.3V.
- Output voltage 1.2V or 1.8V ±4%.
- Output short circuit protection.
- Bundled with Obsidian 1.2V bandgap reference.
- Power down/enable input.
- Fast response to current steps.
Linear regulator, low-noise optimized for sensitive analog loads such as CODEC and Reference
- Starring a PSRR of -65 dB at 20 kHz and a low intrinsic noise, combined with a low quiescent current of 110 uA, the nLR-VAIPO helps optimize the power management network for audio handheld applications such as smartphone and tablet.
- Small footprint: only 0.12 mm2 (including bandgap reference and POK circuit)
- Minimization of the overall system power, through the support of 3 modes of operation: normal, shutdown and bypass
- Eases integration in SoC nLR-VAIPO is delivered with behavioral models. These new views enable to build an optimized Power Management Network (PMNet) by verifying mode transitions as well as noise propagation.
Power on Reset 1.2V
- SMIC 55nm LL technology
- Noise protected
- Low current consumption (~1uA)
LDO