These IPs are targeted at applications requiring high speed, high bandwidth, low-power consumption, and low-latency interfaces.
XPHY Low power Chip to Chip SerDes IP, Silicon Proven in ST 28FDSOI
Overview
Key Features
- Low Power Chip-to-Chip SERDES
- From 10Gb/s to 11Gb/s
- Technology: 28FDSOI 8ML & 10ML
- Platform: 1 Data Slice and 1 Clock Slices
- RX: AC or DC coupling with low-power CTLE
- TX: Power-optimized resistive bridge driver
- Optimized for Low Power Chip-to-Chip SERDES Applications
Benefits
- Ultra low voltage operation
- Optimized for low power Chip to Chip SERDES Applications
Block Diagram
Applications
- IOT
- Wearables
Technical Specifications
Foundry, Node
ST 28FDSOI
Maturity
In Production
Availability
Immediate
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