XAUI XGMII Extender
Overview
The M-XGXS�module from Mentor Graphics provides the physical coding sublayer (PCS) functionality for transfer of Ethernet-based data between a 10-Gbps Ethernet media access controller (MAC) and a SerDes module. Depending on where the MXGXS is instantiated in the data path, the module will be considered a DTE M-XGXS or a PHYM-XGXS. It can support the XAUI interface for incorporation into a customer�s own ASIC design. The M-XGXS module performs all mandatory and optional functionality described in Clause 47 of the IEEE 802.3ae specification. The module is made up of three main sub-modules (as illustrated in the diagram above) and two DDR modules necessary for XGMII traffic. There are many different possible applications for the M-XGXS, including network interface designs, Ethernet switching designs, and test equipment designs.
Key Features
- Fully compliant with IEEE 802.3ae Clause 47
- Supports 802.3ae Clause 45 MDIO interface
- Tolerance oflane skew up to 16ns (50 UI)
- IEEE 802.3ae PICs compliance matrix
- Verified with third party XAUI cores and SerDes
- Supports 802.3ae Clause 48
- Psuedo random idle insertion
- Optional low power mode
- Supports 802.3ae Annex 48Ajitter test pattern
- Supports Altera’s Stratix GX device family
- Supports lane synchronization
- Supports lane to lane alignment
Deliverables
- Verilog source code
- Synthesis constraints files
- Functional testbench
- Expanded Statistics vectors for certain RMON and Etherstats applications