WiMAX Receiver Core is customizable and can be tailored to customer needs.
This decoder is written in VHDL, capable of being used on any FPGA/ASIC architecture.
WiMAX Receiver
Overview
Key Features
- Patented OFDM Synchronization Technology.
- Optimized design allows customers to target cost-efficient FPGAs.
- Can be tailored to customer needs
- Fully synchronous design using only one clock
- Area/Power efficient architecture
Block Diagram
Deliverables
- Netlist or synthesizable RTL source code in VHDL
- Comprehensive verification test bench and vectors in VHDL
- Integration documentation and user guide
Technical Specifications
Related IPs
- WiMAX
- IEEE 802.16e (WiMAX) AES Core
- MIPI CSI-2 Receiver
- DVB-RCS and WiMAX Turbo Decoder with Optional Viterbi Decoder
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