WIDE IO Memory Model

Overview

WIDE IO Memory Model provides an smart way to verify the WIDE IO component of a SOC or a ASIC. The SmartDV's WIDE IO memory model is fully compliant with standard WIDE IO Specification and provides the following features. Better than Denali Memory Models.

WIDE IO Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

WIDE IO Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

Supports WIDE IO memory devices from all leading vendors.
Supports 100% of WIDE IO protocol standard JESD229.
Supports all the WIDE IO commands as per the specs.
Quickly validates the implementation of the WIDE IO standard JESD229.
Supports Programmable burst lengths: 2, 4.
Checks for following

Check-points include power up, initialization and power off rules
State based rules, Active Command rules
Read/Write Command rules etc.,
All timing violations

Supports All Mode registers programming.
Supports Write data Mask.
Supports Power Down features.
Supports input clock stop and frequency change.
Supports full-timing as well as behavioral versions in one model.
Supports all timing delay ranges in one model: min, typical and max.
Constantly monitors WIDE IO behavior during simulation.
Protocol checker fully compliant with WIDE IO Specification JESD229.
Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
Built in functional coverage analysis.
Supports Callbacks, so that user can access the data observed by monitor.

Benefits

Faster testbench development and more complete verification of WIDE IO designs.
Easy to use command interface simplifies monitor control and configuration.
Simplifies results analysis.
Runs in every major simulation environment.

Block Diagram

Deliverables

Complete regression suite containing all the WIDE IO testcases.
Examples showing how to connect and usage of Model.
Detailed documentation of all class, task and function's used in verification env.
Documentation also contains User's Guide and Release notes.

Technical Specifications

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