The Digital Blocks DB-SPI-FLASH-CTRL is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting access to Single/Dual/Quad SPI Flash Memory devices by way of Boot, Execute-in-Place (XIP), Processor Memory-Mapped IO, or optional DMA.
The DB-SPI-FLASH-CTRL contains an AHB Slave Interconnect allowing for Memory Read of Flash Memory via the SPI Master Bus, and an AHB-Lite, AHB, or APB Slave Interface for Processor Configuration and Memory Read/Write of Flash Memory.
AXI / AHB / APB - SPI Flash Memory Controller - Octal/Quad/Dual/Single SPI I/O - CPU access to Flash and optional Execute-in-Place (XIP), Boot, DMA
Overview
Key Features
- Master SPI Controller Targeting SPI Flash Memory Access
- SPI Flash Memory:
- Supports CPU access of SPI Flash memory
- Boot, Execute-In-Place (XIP), and DMA (optional features)
- Flash Memory from Adesto, Cypress/Spansion, Macronix, Micron, and Winbond
- Supports SPI Mode0, Mode3 at 166 MHz
- Up to N=8 Slave Select (SS) Outputs supporting multiple SPI Flash Memory devices
- Configurable SPI Modes:
- Standard SPI Mode (1 Data Lane)
- Dual SPI Mode (2 Data lanes)
- Quad SPI Mode (4 Data Lanes)
- Octal SPI Mode (8 Data Lanes)
- Programmable LSB-first or MSB-first Per Word
- Transmit/Receive FIFOs:
- Dual-Clock designs
- User configurable depths
- Two Clock Domains:
- AMBA Bus / SCK Clocks
- Internal interrupts with masking control
Deliverables
- Verilog RTL Source or technology-specific netlist.
- Comprehensive testbench suite with expected results.
- Synthesis scripts.
- Installation & Implementation Guide.
- Technical Reference Manual.
Technical Specifications
Foundry, Node
Chartered, IBM, LSI. OKI, Silterra, SMIC, STMicroelectronics, Tower, TMSC, UMC
Maturity
Successful in Customer Implementations
Availability
Immediately
Related IPs
- Fast Access Controller – a plug-and-play IP solution for fast embedded Flash Programming and Memory Testing
- SPI FLASH Controller with Execute in place – XIP (SINGLE, DUAL and QUAD SPI Bus Controller with DDR / DTR support and optional AES Encryption)
- Single, Dual and Quad SPI Flash Controller with Boot and Execute On-The-Fly Features
- QSPI FLASH Controller – XIP functionality (SINGLE, DUAL and QUAD SPI Bus Controller with Double Data Rate support)
- eSPI & SPI Master/Slave Controller w/FIFO (APB, AHB, or AXI Bus)
- Octal SPI Controller – XIP functionality (SINGLE, DUAL, QUAD and OCTAL SPI Bus Controller with Double Data Rate support) and DMA Support