IP Catalog > Peripheral IP > Timer/Watchdog IP > WATCHDOG IIP

WATCHDOG IIP

Overview

Watchdog is used to generate system reset in case of software or hardware failures when the main program doesn't reset it's counter periodically, compatible with standard protocol of Watchdog specification. Through its Watchdog compatibility, it provides a simple interface to a wide range of low-cost devices. Watchdog IIP is proven in FPGA environment.The host interface of Watchdog can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.

WATCHDOG IIP is supported natively in Verilog and VHDL

Key Features

  • Supports to prevent system lock up due to software anomalies or hardware failure
  • Supports cold reset after configured interval
  • Supports interrupt indication after programmed time period
  • Supports both firmware and hardware pause and resume
  • Supports to restart watchdog timer via software interface
  • Supports 32 bit counter to count a maximum value of 32’hFFFFFFFF.
  • Automatically reload value support.
  • Supports to hold count value.
  • Supports enabling and disabling of interrupts.
  • Fully synthesizable.
  • Static synchronous design.
  • Positive edge clocking and no internal tri-states.
  • Scan test ready.
  • Simple interface allows easy connection to microprocessor/microcontroller devices.

Benefits

  • Single Site license option is provided to companies designing in a single site.
  • Multi Sites license option is provided to companies designing in multiple sites.
  • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
  • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

Block Diagram

WATCHDOG IIP Block Diagram

Deliverables

  • The Watchdog interface is available in Source and netlist products.
  • The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
  • Easy to use Verilog Test Environment with Verilog Testcases
  • Lint, CDC, Synthesis, Simulation Scripts with waiver files
  • IP-XACT RDL generated address map
  • Firmware code and Linux driver package
  • Documentation contains User's Guide and Release notes.

Technical Specifications

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