The CMS0002 Viterbi Decoder core implements Viterbi’s algorithm for maximum likelihood decoding of non-feedback convolutional codes. Applications include DOCSIS (J.83B), DVB T, 802.11a and 802.16.
The basic 1/2 rate convolutional encoder and decoder are shown above. For each input bit, two encoded bits are produced. The rate can be increased to 2/3, 3/4, 5/6, or 7/8 by non transmission (puncture) of certain bits. Punctured codes lose coding gain as the redundant content decreases.
The encoded X and Y bits are transmitted through a noisy channel. The received X and Y values are measured then presented as soft decision values to the decoder.
Zero Flush
Both 802.11a and 802.16 specify this mode of operation. With this approach, the convolutional encoder is guaranteed to be in state zero at both the beginning and end of the burst. This is especially important at the end of the burst because there is no further history to trace back from.
To support this mode, state metrics are initialised at the beginning of the burst such that all possible successor states will ultimately be based on state 0. A description of the processing steps follows:
- State Metric Unit. This block maintains a measure of probability for each possible encoder state. As each soft pair is processed, the SMU produces the most likely received data bit for each state (the Branch Data vector).
- Traceback Unit. This block provides a history of most likely state transitions. This allows traceback from any current state to ever more likely predecessor states.
After a certain depth the optimum state becomes known and traceback from this point produces reliable data. The required minimum traceback depth depends on the code parameters, puncture rate and soft-decision width.
At the end of the burst, extra zeros are appended to the data stream to flush the encoder to its known final state of 0. The known final state gives a valid starting point for traceback in the decoder. When the CodeBlockActive input goes to zero, the decoder forces a final state of zero and begins traceback of the data.
Memory Configuration
The core uses a novel memory architecture for the Traceback Unit. Traceback is performed in chunks of configurable size. These are arranged in a ring with each slice receiving a Best End State and producing a Best Initial State. The number of traceback slices (TBS) varies depending on ChunkSize and TBlength.
This allows separate optimisation for FPGA or ASIC. Often ASIC memory has a large minimum size (e.g. 64 words) with each RAM cell requiring individual attention and consequently a small number of larger RAM cells are appropriate.
Conversely, for FPGA applications, RAMs may be built from logic cells and the total bit count may be minimised by using a larger number of small RAM cells.
Note, that the total group delay through the decoder is reduced by using smaller ChunkSize. Refer to the Synthesis Controls section for further information
