Very High Speed 8 State MAP Decoder

Overview

Key Features

• 8 state soft-in-soft-out (SISO) maximum a posteriori (MAP) triple interleaved error control decoder and systematic recursive convolutional encoder
• Up to 120 Mbit/s decoding speed for all states
• Rate 1/2, 1/3, or 1/4 with optional punctured inputs
• 6-bit received data, 8-bit soft-in and soft-out data for information and parity bits for all rates
• 8-bit branch metric inputs for rate 1/2
• Optional code polynomials
• Optional block decoding with or without tail
• Optional max-log-MAP or log-MAP algorithm with 9 or 17 programmable SNR's
• Continuous sliding block algorithm with sliding block lengths of 32 or 64
• Low decoding delay (398 or 782 CLK cycles)
• No external RAM required
• Asynchronous logic free design
• Ideal for iterative decoding of 3GPP turbo codes
• Low power mode and synchronous reset
• Available as EDIF/VHDL cores or BIT/MCS files for download into Xilinx Virtex, Virtex-E, Virtex-II, Spartan-II, and Spartan-IIE FPGAs. Actel, Altera and Lattice FPGA cores available on request.
• Support for ASIC cores is also available
• 3GPP is a trademark of ETSI

Deliverables

• EDIF core
• VHDL simuluation core
• Test vector generation software

Technical Specifications