The A2FM product is a collection of floating-point execution units compliant with the ANSI/IEEE Std 754-1985, IEEE Standard for Binary Floating-Point Arithmetic (IEEE-754 Standard). The units are designed for high frequency, high throughput implementations. Each unit is implemented as a state less pipeline that can easily be integrated into a high-performance processor design.
Each unit is targeted for a clock cycle with only 10-12 gate delays (excluding setup and clock skew). The add and multiply units implement 5-cycle pipelines. The conversion unit implements a 2-cycle pipeline, and the compare unit a 1-cycle pipeline. All units can sustain a 1-cycle throughput. The multiply unit supports fused floating-point multiply add, as well as a variety of 32-bit integer multiply functions.
IEEE-754 Compliance
The A2FM modules are designed to provide a powerful floating-point capability while minimizing die size cost. To minimize unnecessary design size, some of the rarely used features of the IEEE specification are not implemented directly in the hardware design. The following IEEE-defined operations are not directly supported in A2FM hardware, but can be supported with software support:
- Gradual Underflow
- Denormal Numbers
In place of gradual underflow, the A2FM modules implement a flush-to-zero approach when underflow occurs. This feature allows the A2FM modules to maintain a one-cycle throughput in all operand cases, and minimizes design size.
