VeriSilicon SMIC 0.13umLL 1P3M High-Density Synchronous Single-Port SRAM compiler, Memory Array Range:128 to 512K Bits
Overview
VeriSilicon SMIC 0.13umLL 1P3M High-Density Synchronous Single-Port SRAM compiler optimized for Semiconductor Manufacturing International Corporation (SMIC) 0.13um Low Leakage 1P3M Salicide 1.5/2.5(3.3)V process can flexibly generate memory blocks via a friendly GUI or shell commands. The compiler supports a comprehensive range of words and bits. While satisfying speed and power requirements, it has been optimized for area efficiency. VeriSilicon SMIC 0.13?mLL 1P3M High-Density Synchronous Single-Port SRAM compiler uses three layers within the blocks and supports metal 3 as the top metal. Dummy bit cells are designed in with the intention to enhance reliability.
Key Features
- Single Read/Write Port
- High Density
- Margin controllable for yield improvement
- Size Sensitive Self-Time Delay for Fast Access
- Automatic Power Down
- Write Mask Function
Technical Specifications
Foundry, Node
SMIC 0.13um LL
Maturity
Pre-Silicon
SMIC
Pre-Silicon:
130nm
LL
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