VeriSilicon SMIC 0.13um 1.2V/2.5V ANALOGIO_DUP_05 IO Library
Overview
VeriSilicon SMIC 0.13um 1.2V/2.5V ANALOGIO_DUP_05 IO library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporation (SMIC) 0.13um Logic 1P8M Salicide 1.2/2.5V process. This library provides 5V analog IO pads. This library supports Device Under Pad (DUP).
Key Features
- SMIC 0.13um Logic 1P8M Salicide 1.2/2.5V process
- Provides 5V analog IO pads
- Supports Device Under Pad (DUP)
- Provides cells to interface with Generic IO library
- Suitable for six, seven, or eight metal layers of physical design
Deliverables
- Databook in electronic form
- Verilog models and Synopsys synthesis models
- Cadence Silicon Ensemble Abstracts (LEF), Avanti! Apollo data, GDS II, LVS netlist
Technical Specifications
Foundry, Node
SMIC 0.13um
SMIC
Pre-Silicon:
130nm
EEPROM
,
130nm
G
,
130nm
LL
,
130nm
LV
Related IPs
- VeriSilicon SMIC 0.13um 1.2V/2.5V OSC
- SMIC 0.13um General Process, 1.2V/2.5V Standard Cell Library
- SMIC 0.13um High Vt Process, 1.2V/2.5V standard cell Library
- VeriSilicon CHRT 0.13um 1.2V/2.5V DUPIO_01 Library
- VeriSilicon TSMC 0.13¦Ìm 1.2V/2.5V DUPIO_01 Library
- VeriSilicon SMIC 0.13¦Ìm 1.2V/3.3V ANALOGIO_DUP_05 IO Library