VeriSilicon CHRT 0.13um 1.2V/2.5V DUPIO_01 Library

Overview

VeriSilicon CHRT 0.13um 1.2V/2.5V DUP I/O Cell Library developed by VeriSilicon is optimized for Chartered Semiconductor Manufacturing (CHRT) 0.13um Logic 1P8M Salicide 1.2/2.5V process. This library supports Device Under Pad (DUP). This library includes analog I/O cell part and digital I/O cell part, and the digital I/O cells can take 3.3V tolerance and work with configurable and variable driving strength between 2mA - 24mA. This library supports Inline I/O pad.

Key Features

  • CHRT 0.13um Logic 1P8M Salicide 1.2V/2.5V process
  • Low area and low cost design using DUP technique
  • 1.2V core power, 2.5V IO, digital IO supports 3.3V tolerance
  • This library includes analog I/O cell part
  • Configurable output driving capability with different slew rate
  • Supports configurable pull up and pull down resistor
  • Supports both CMOS input and Schmitt input with LVTTL compatible
  • Provides 2Mhz ~ 27Mhz OSC IO cell
  • Suitable for six, seven, or eight metal layers of physical design
  • Competitive pad pitch and height

Deliverables

  • Databook in electronic form
  • Verilog models and Synopsys synthesis models
  • Cadence Silicon Ensemble Abstracts (LEF), Avanti! Apollo data, GDS II, LVS netlist

Technical Specifications

Foundry, Node
CHRT 0.13um
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Semiconductor IP