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General-Purpose I/O (GPIO) IP

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Compare 580 General-Purpose I/O (GPIO) IP from 30 vendors (1 - 10)
  • 1.8V/3.3V I/O Library with 5V ODIO & Analog in TSMC 16nm
    • A Flipchip I/O Library with dynamitcally switchable 1.8V/3.3V GPIO, 5V I2C/SM- Bus ODIO, 5V OTP Cell, 1.8V & 3.3V Analog Cells and associated ESD.
    • A key attribute of this library is its ability to detect and dynamically adjust to a VDDIO supply of 1.8V or 3.3V during system operation.
    Block Diagram -- 1.8V/3.3V I/O Library with 5V ODIO & Analog in TSMC 16nm
  • 1.8V/3.3V I/O library with ODIO and 5V HPD in TSMC 16nm
    • A 1.8V/3.3V flip-chip I/O library with 4kV HBM ESD protection, I2C compliant ODIO and Hot-Plug Detect.
    • This library is a production-quality, silicon-proven I/O library in TSMC 16nm technology.
    • Supports multi-voltage GPIOs, capable of operating at 1.8V or 3.3V, dynamically selectable at the system level.
    Block Diagram -- 1.8V/3.3V I/O library with ODIO and 5V HPD in TSMC 16nm
  • 1.8V/3.3V I/O Library with ODIO and 5V HPD in TSMC 12nm
    • A 1.8V/3.3V flip-chip I/O library with 4kV HBM ESD protection, I2C compliant ODIO and Hot-Plug Detect.
    • This library is a production-quality, silicon-proven I/O library in TSMC 12nm technology.
    • Supports multi-voltage GPIOs, capable of operating at 1.8V or 3.3V, dynamically selectable at the system level.
    Block Diagram -- 1.8V/3.3V I/O Library with ODIO and 5V HPD in TSMC 12nm
  • 1.8V to 5V GPIO, 1.8V to 5V Analog in TSMC 180nm BCD
    • A Flip-Chip compatible I/O Library in TSMC 180nm BCD with 1.8V to 5V GPIO, 1.8V to 5V analog, with ultra low-cap/low-leakage RF solutions.
    • This silicon proven flip-chip compatible library in TSMC 180nm BCD features a multi-voltage GPIO, 1.8V to 5V analog I/O, and ultra-low capacitance and low leakage 36V+ ESD solutions. The library also includes 5V RF pads.
    Block Diagram -- 1.8V to 5V GPIO, 1.8V to 5V Analog in TSMC 180nm BCD
  • 1.8V GPIO, 1.8V to 3.3V Analog in TSMC 180nm BCD
    • A Flip-Chip compatible I/O Library in TSMC 180nm BCD with 1.8V GPIO, 1.8V to 3.3V Analog, with ultra low-cap/low-leakage 36V+ ESD solutions.
    • This silicon proven flip-chip compatible library in TSMC 180nm BCD features a 1.8V GPIO, 1.8 to 3.3V analog I/O, and ultralow capacitance and low leakage 36V+ ESD solutions.
    Block Diagram -- 1.8V GPIO, 1.8V to 3.3V Analog in TSMC 180nm BCD
  • 1.8V/3.3V GPIO Library with HDMI, Aanlog & LVDS Cells in TSMC 22nm
    • A TSMC 22nm Inline, Flip Chip compatible library with GPIO, ODIO, HDMI, LVDS, & Analog Cells.
    • This silicon-proven, flip chip compatible library in TSMC 22nm boasts a two speed GPIO: 75MHz and 150MHz.
    • The library also features a 5V ODIO. GPIO and ODIO cells have an orientation of NS and EW.
    Block Diagram -- 1.8V/3.3V GPIO Library with HDMI, Aanlog & LVDS Cells in TSMC 22nm
  • 0.9V/1.2V I/O Library in TSMC 55nm
    • A 0.9V/1.2V I/O Library in TSMC 55LP.
    • This SoundWire Digital I/O Library in TSMC 55nm LP offers an advanced, low-power interface solution for high-performance audio applications.
    • Supporting 0.9V/1.2V operation, this library provides Data, Clock, and Select I/Os, enabling seamless integration with SoundWire-based systems while delivering enhanced power efficiency.
    Block Diagram -- 0.9V/1.2V I/O Library in TSMC 55nm
  • 1.8V GPIO, 1.8V & 3.3V Analog in TSMC 180nm BCD
    • The silicon-proven I/O library in TSMC 180nm BCD provides a reliable and flexible solution for mixed-signal, power management, and BCD applications.
    • The library includes a 1.8V digital I/O cell, optimized for up to 100MHz operation at 15pF, ensuring efficient high-speed performance.
    • It also features 1.8V and 3.3V baseline analog I/Os, along with custom low-leakage 3.3V analog I/Os, tailored for low-power and precision-driven designs.
    Block Diagram -- 1.8V GPIO, 1.8V & 3.3V Analog in TSMC 180nm BCD
  • Multi-Voltage GPIO 5V ODIO and Analog/RF I/Os in TSMC 65nm
    • Key attributes of this IO library include dual independent IO supply rails (1.0V-3.3V 3.3V) and power-on-control (POC) to place IOs in HiZ during power-down.
    • The GPIO cell can be configured as input, output or open-drain with a Schmitt trigger input and optional internal 55K ohm pull-up or pull-down resistor.
    • Cells for two independent IO supplies, core power, ground and isolated ground with built-in ESD are included.
    Block Diagram -- Multi-Voltage GPIO 5V ODIO and Analog/RF I/Os in TSMC 65nm
  • 1.8V/3.3V GPIO Compliant with Multiple Standards in TSMC 16nm
    • This library is a high-voltage GPIO I/O Macro in TSMC 16nm.
    • The high-voltage GPIO is a flip-chip compatible 1.8V to 3.3V GPIO design, compliant with multiple I/O standards.
    • It comes as a macro cell with a pair of I/Os in each cell, allowing differential I/O interface capabilities as well.
    Block Diagram -- 1.8V/3.3V GPIO Compliant with Multiple Standards in TSMC 16nm
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