VDC-M (VESA Display Compression-M) Decoder

Overview

The Rambus VESA VDC-M 1.2 Decoder IP Core (formerly from Hardent) implements a fully compliant VESA Display Compression-M (VDC-M) 1.2 decoder to deliver visually lossless video compression. The decoder supports various usage models, including typical MIPI Display Serial Interface 2 (MIPI DSI-2) usage models.

Key Features

VESA Display Compression-M (VDC-M) 1.2 compliant
Supports all VDC-M encoding mechanisms

BP, transform, MPP, MPP fallback, and BP skip
Flatness detection and signalling

Confgurable maximum display resolution of up to 16Kx16K

Typical 4K (4096x2160), 5K UHD+, and 8K UHD supported

8, 10, or 12 bits per component video
4:4:4 samples for RGB video output format
4:4:4, 4:2:2, and 4:2:0 samples for YCbCr video output formats
Parameterizable number of parallel slice decoder instances
(1,2 or 4) to adapt to the capability of the technology and target
display resolutions used
Supports logical slice decoding (soft slice) in each physical decoder
(hard slice)
Ultra-low latency
Pixel throughput of four pixels per clock per hard slice decoder
Optimized for power savings

Block Diagram

Applications

Mobiles & Tablets
AR/VR Products
MIPI DSI-2 Applications
Automotive Video Transmission

Deliverables

Encrypted RTL source code IP core
Functional and structural coverage reports
Comprehensive integration guide

Technical Specifications

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