VBO TX and RX PHY & Controller

Overview

The VBO IP is designed for transmitting or receiving video signals between a video source device and display device, which is fully compliant with VBO1.4 specifications. The IP provides both PHY and controller solutions, offering a reliable implementation for VBO interface that can be seamlessly integrated into the SoCs used in multimedia devices.

The VBO TX IP transmits video and control data from a video source device to a display device. It consists of a digital controller and a physical layer. The digital controller processes the input video, control data, and timing data, with pixel clock frequencies. The physical layer includes data channels, PLL, and a bias circuit, supporting data rates of up to 4Gbps per lane.

The VBO RX IP receives and recovers video and control data from the VBO source device. It comprises a physical layer and a digital controller. The physical layer includes data lanes, each featuring termination, an equalizer, and a clock data recovery (CDR) circuit to ensure robust signal reception. The digital controller processes the recovered video data through 10b/8b decoding, descrambling, and unpacking, converting it into video data, control data and timing data.

Key Features

  • Compliant with V-by-One HS Standard Version 1.4
  • Supports 1/2/4/8/16-lane configuration
  • Supports 3/4/5-byte mode
  • Supports data rates up to 4Gbps per data lane
  • Supports display resolution up to 4K/60Hz
  • Supports AC-coupled input and termination connected to ground
  • Supports automatic termination resistance
  • Supports pixel clock frequency from 20MHz to 600MHz
  • Supports programmable termination, swing, and equalization
  • Supports SSC modulation
  • Supports BIST logic
  • APB slave interface for internal register access
  • Built-in low jitter PLL and bandgap reference
  • The area and power consumption correlate strongly with process node and data lane counts. please refer to the detailed datasheet

Benefits

  • Low power consumption
  • Fully customizable
  • Small area
  • Simple integration process
  • Available options include
    • Test chips and test boards
    • FPGA integration support
    • Chip level integration

Block Diagram

VBO TX and RX PHY & Controller Block Diagram

Applications

  • Consumer Electronics
  • Automotive
  • Industrial Automation
  • Medical Devices
  • Gaming

Deliverables

  • Datasheet
  • Timing Library Model (LIB)
  • Encrypted Verilog Model
  • Library Exchange Format (LEF)
  • GDSII Database
  • Evaluation Board if Available

Technical Specifications

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