V-By-One Transmitter IIP

Overview

VBYONE Transmitter core is compliant with standard VByOne specification as 1.2/1.3/1.4. Through its compatibility, it provides a simple interface to a wide range of low-cost devices. VBYONE Transmitter IIP is proven in FPGA environment. The host interface of the VBYONE can be AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses.

V-By-One Transmitter IIP is supported natively in Verilog and VHDL

Key Features

Compliant with VByOne specification 1.2/1.3/1.4.
Full VBYONE Transmit functionality.
Supports 1 to 8 lanes. If needed, we can support custom lane configuration.
Supports all byte lengths.
Supports all color depths.
Supports all resolutions.
Supports 8b/10b Encoding.
Supports 10 bit, 20 bit ,40 bit parallel serdes interface.
Supports scrambler as in VByone HS specification.
Supports color data mapping allocation to 3D flag.
Supports control data mapping allocation to 3D flag.
Supports 1 lane data with 1 section allocation in frame.
Supports 2 lane data with 1 section allocation in frame.
Supports 2 lane data with 2 section allocation in frame.
Supports 4 lane data with 1 section allocation in frame.
Supports 4 lane data with 2 section allocation in frame.
Supports 4 lane data with 4 section allocation in frame.
Supports 8 lane data with 1 section allocation in frame.
Supports 8 lane data with 2 section allocation in frame.
Supports 8 lane data with 4 section allocation in frame.
Supports 8 lane data with 8 section allocation in frame.
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready
Simple interface allows easy connection to microprocessor/microcontroller devices

Benefits

Single site license option is provided to companies designing in a single site.
Multi sites license option is provided to companies designing in multiple sites.
Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

Block Diagram

Deliverables

The VBYONE Transmitter interface is available in Source and netlist products.
The Source product is delivered in plain text verilog. If needed VHDL,SystemC code can also be provided.
Easy to use Verilog Test Environment with Verilog Testcases
Lint, CDC, Synthesis, Simulation Scripts with waiver files
IP-XACT RDL generated address map
Firmware code and Linux driver package
Documentation contains User's Guide and Release notes.

Technical Specifications

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