The USB 2.0 PHY is a Hi-Speed USB peripheral transceiver IP that implements the Intel® UTMI standard. It provides a High/Full/Low-Speed USB analog front-end with a build-in 8-bit/16-bit parallel interface. It is optimized for portable applications with low power dissipation while active and/or standby, and small area for low cost. The USB 2.0 PHY can be implemented as a discrete or integrated physical layer interface for any OTG device that complies with the On-The-Go and Embedded Host Supplement to the USB Revision 2.0 Specification, or any host or peripheral that complies with the USB 2.0 specification. It also supports battery charging function.
USB2.0 PHY
Overview
Key Features
- Silicon proven in 22, 28, 40, 55, 65, 110, 130, 180nm from SMIC, GlobalFoundries and Samsung
- Low power dissipation while active, idle, or suspend
- Compliant with the USB Spec Rev2.0/s
- Compliant with the UTMI+ Spec Rev1.0 Level3
- Compliant with the On-The-Go (OTG) Spec Rev2.0
- Supports 480Mbit/s “High Speed”, 12Mbit/s “Full Speed” and 1.5Mbit/s “Low Speed”
- Compliant with the UTMI Spec Rev1.05
- Compliant with the Battery Charging Spec Rev1.1
- Supports 60MHz/8-bit interface and 30MHz/16-bit interface
- Integrates 45Ω±10% termination, 1.5kΩ pull-up
- And 15KΩ pull-down resistor
Block Diagram
Technical Specifications
GLOBALFOUNDRIES
Pre-Silicon:
22nm
,
28nm
Samsung
Pre-Silicon:
28nm
LPP