USB 3.1 Cable Marker IP

Overview

Key Features

• USB PD 3.1 compliant.
• Single chip solution – just two external capacitors.
• 4 pin package.
• Less than 1mm2 area in 180nm.
• PROM programmed through vendor message protocol.
• Based on Obsidian’s mature PD technology.
• Integrated PROM enables customized response to a wide range of vendor requirements.
• Active Ra pulls down only requires 10uA at 5V., but is <1K below 2V.
• Power <5mW. Enabled by CC data activity. I.e. very low duty cycle.
• Programming can be done after assembly into the cable. Fuse lock function.
• Supports low cost, 4 layer PCB assembly.
• Supported by the module level test program.
• Package options: WLCSP-4, QFN-8, DFN-8, SOP23-5.
• IP licensing is available.

Benefits

• Physical Layer. Based on Obsidian’s OTC9107 port chip physical layer, this provides CC line driving and reception without external components. It includes data slicer, activity detection, voltage level detection, and slew rate controlled driver.
• LDO. Provides bandgap, and internal voltage regulation for the logic the physical layers. Power diodes also provide the required power isolation between two possible power sources (one at each end of the cable).
• Oscillator. A low temperature drift 12MHz oscillator provides logic clocking when required. The provided test program automatically trims the oscillator during a test for an overall frequency accuracy of ±5%.
• Protocol Engine implements the low level protocol and logic PHY functions required by the standard. Such as CRC generation and testing, 4b5b coding, BMC coding, clock recovery, and SERDES.
• Marker State Machine. Provides the subset of device functions required to recognize vendor messages and return responses based on PROM data.
• Programmed response. Will respond with Cert-Stat VDO and Cable-VDO with all relevant fields programmable.
• Supporting Software in C form is available for rapid implementation of production test.

Block Diagram

Applications

• Power supply
• Bus powered devices
• Automotive

Deliverables

• PHY: GDS, verilog model, design review.
• RTL: with Back to back port simulation harness.
• C source code for port policy engine and device policy manager.
• C source code for Windows demo control application.
• Data sheet.
• Compliance test results from demo board.
• Pre sale on-line source walk-through.
• Demo Board: with installed software, and power supplies for back to back system testing, and for use in compliance testing.
• Optional ATE vectors.
• Optional supporting functions include on-chip oscillators, references, and slave I2C.

Technical Specifications