USB 2.0 OTG High/Full/Low-Speed Dual Role Core

Overview

Key Features

• Fully compliant to USB Specification 2.0 and the On-The-Go Supplement, Revision 1.0
• Fully compliant to UTMI Specification 1.05 and UTMI+ Specification 1.0 up to UTMI+ level 3
• Fully compliant to UTMI+ Low Pin Interface Specification 1.0
• High-/Full-/Low-Speed device and host capability (480Mbps/12Mbps/1.5Mbps)
• 60 MHz (for 8 bit UTM interface) or 30 MHz (for 16 bit UTM interface) system clock
• Supports OTG Host Negotiation Protocol (HNP)
• Supports OTG Session Request Protocol (SRP)
• Scalable number of pipes , up to 32 pipes are supported
• Configurable for 16 or 32 bit register and data interface (64 bit in preparation)
• Extended Transaction Manager, enables the realization of systems with a minimum of software overhead
• Supports all transfer types (Control, Interrupt, Isochronous, Bulk)
• Pipe direction, transfer type and FIFO size can be configured during run-time
• Supports hardware based schedulung and enhanced large buffer management
• Automatic retry for corrupted data packets
• Automatic split transaction management
• PCI ready
• AMBA AHB ready (AHB slave interface for configuration, AHB master DMA interface or AHB slave
• interface with Dual-Port RAM for payload data)
• AHB interface testet with Synopsys Amba Verification Suite
• Alternatively, Dual-Port RAM interface available with scalable memory size
• Suspend/Resume/Remote Wakeup support
• Technology independent, fully synchronous RTL implementation
• PCI evaluation module available
• Generic USB Device Software Stack with several class drivers available
• Generic USB Host Software Stack with several class drivers available
• Optional: EHCI, OHCI and UHCI software emulation for host mode available
• With the features described above, the FHG USB2 OTGDRD brings an USB interface to your system, which is highly efficient from software’s point of view:
• All USB related timing critical features are realized in hardware. Therefore, for normal operation software has only to manage the enumeration process
• Once a pipe or channel is established, the only task of the software is to provide data buffers (entire USB protocol is managed by hardware, including data toggle, retry, polling of periodic pipes, ping protocol, split protocol) This reduces the number and frequency of software interrupts to an minimum.
• The required interrupt latency time does not depend on the timing required by the USB packet level, but on the size of data buffers and pipe bandwidth

Benefits

• Typical USB devices working with the USB 2.0 OTG Dual Role Controller Core are for example hard disk devices, multimedia devices, mobile phones, imaging devices, high speed network or industrial applications which require high bandwidth, low latency data transport.

Deliverables

• One of the following LICENSES:
• VHDL source code for ASIC designs
• Synopsys Design Ware Component for ASIC designs
• VHDL/Verilog Netlist for FPGA designs (Xilinx/Actel/Altera)
• (Other license models upon request)
• The DESIGN KIT contains the following parts:
• The IP component, depending on the selected license
• VHDL/Verilog pre-compiled simulation models
• VHDL/Verilog USB 2.0 compliance test suite
• IP integration guideline
• Synthesis scripts
• Optional:
• PCI evaluation board

Technical Specifications