The USB 2.0 Host Controller (USB20HC) IP Core is a 32-bit Avalon interface compliant core and supports ULPI interface. The core supports High Speed (480 Mbit/s) mode, Full Speed (12 Mbit/s) mode and Low Speed (1.5 Mbits/s) mode operation.
The core has been optimized for popular FPGA devices and its functionality has been verified on the hardware. It is provided as Altera Quartus II Mega function (Altera SOPC Builder and Qsys ready component) and can be integrated easily into any SOPC Builder and Qsys generated system using Avalon bus.
USB 2.0 Host Controller
Overview
Key Features
- Supports Low Speed (1.5 Mbps), Full Speed (12 Mbps) and High Speed (480 Mbps)
- Supports UTMI+Low Pin Interface (ULPI)
- Supports ULPI PHY low power mode and register access through software
- Supports 15 Bulk and 2 Interrupt Endpoints
- Performs all USB enumeration process through software and CRC calculation through Hardware
- Avalon Bus Complaint
- Optimized LE count
- IP Core has been tested by interfacing it with USB 2.0 PHY (RN1133) on SLS HSIC development board
- It has also been verified under simulation environment.
Benefits
- 30 Day free evaluation
- Direct support from IP design Engineers
- System development support available
- Hardware (PCB) development support available
- Software and application development support also available
Deliverables
- Evaluation Version
- USB 2.0 Host Controller encrypted IP core
- One (1) month evaluation license at no cost (from the License Request page )
- Reference Design
- Demonstration file
- Windows Driver (Object File)
- Windows Application
- Reference Documents
- HAL driver with Application
- Full Version
- USB 2.0 Host Controller encrypted IP core
- Perpetual license
- Reference Design
- Demonstration file
- Windows Driver (Object File)
- Windows Application
- Reference Documents
- HAL driver with Application
Technical Specifications
Availability
Now