UMC L40LP 40nm Clock Generator PLL - 300MHz-1500MHz

Overview

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It contains a 1-32 divider at the reference clock input, a 1-4096 divider in the internal feedback path, and a 1-8 divider at the output. The outputs are 50% duty cycle for all output divider values.

Key Features

  • Designed as a very flexible clock multiplier capable of multiplying an input clock from 1 to 4096 with very small period jitter while operating at the highest possible bandwidth.
  • Delivers optimal jitter performance over all multiplication settings.
  • Available with multi-phase outputs and, in some processes, with an I/O voltage regulator.
  • Ideal for system clock generation, SerDes and video clock applications.

Deliverables

  • GDSII (100% DRC and LVS clean)
  • LVS Spice netlist
  • Verilog model
  • Synopsys synthesis model
  • LEF for clock generator PLL
  • User Guidelines including:
    • integration guidelines,
    • layout guidelines,
    • testability guidelines,
    • packaging guidelines,
    • board-level guidelines

Technical Specifications

Foundry, Node
UMC L40LP
UMC
Pre-Silicon: 40nm LP
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Semiconductor IP