UMC 55nm ULP/LowK Process Single-Port SRAM with RED Well Biase Memory compiler
Overview
UMC 55nm ULP/LowK Process Single-Port SRAM with RED Well Biase Memory compiler
Technical Specifications
Foundry, Node
UMC 55nm
UMC
Pre-Silicon:
55nm
Related IPs
- UMC 55nm ULP/LowK Process Single-Port SRAM with well bias & RED Memory Compiler
- Single Port SRAM compiler - Memory optimized for high density and low power - Deep N Well supported - compiler range up to 320 k
- High performance 8-bit micro-controller with 256 bytes on-chip Data RAM, three 16-bit timer/counters, and two 16-bit dptr; 0.25um UMC Logic process.
- UMC 55nm ULP/LowK Process Single-Port SRAM with well bias HVT Memory Compiler
- UMC 55nm ULP/LowK Single-Port SRAM with Well Bias uHVT
- Silterra 0.11um High Density Single-Port SRAM Compiler