UltraFast BCH Decoder

Overview

BCH codes are widely used where bit errors are scattered randomly within the codeword. The Creonic Ultrafast BCH Decoder is capable of processing an entire BCH codeword per clock cycle in a pipelined way. Therefore, tt achieves outstanding data rates.

The design can be parameterized at design-time to support different codeword sizes and code rates. Latency can be adjusted by insertion or removal of pipeline register stages.

Key Features

Coded throughput of up to 163.5 Gbit/s at 320 MHz (FPGA, 511 codeword bits)
Coded throughput of up to 122.4 Gbit/s at 480 MHz (FPGA, 255 codeword bits)
Latency in the range of 4 to 14 clock cycles (466 payload bits, 511 codeword bits)

Benefits

Throughput of one codeword per clock cycle
Fully pipelined design
Design-time configuration of BCH code size and code rate
Design-time configuration of primitive polynomial
Design-time configuration of latency for optimal resource utilization
Bit error rate measurement
Low-power and low-complexity design
Available for ASIC and FPGAs (AMD Xilinx, Intel, Microchip)

Applications

Die-to-die communication
Free-space optical (FSO) communication
Further applications with the need for tremendous data rates

Deliverables

VHDL or Verilog source code or synthesized netlist
HDL simulation models e.g. for Aldec's Riviera-PRO
VHDL testbench
bit-accurate Matlab, C or C++ simulation model
comprehensive documentation

Technical Specifications

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