Ultra-speed FIR Filter

Overview

FIR filter designed for very high sample rate applications. Organized as a systolic array, the filter is modular and scalable, permitting the user to specify large order filters without compromising maximum attainable clock-speed.

Matlab®, FDAtool and Simulink® compatible.

Key Features

  • Systolic array for speed and scalability
  • Configurable coefficients
  • Configurable data width
  • Configurable number of taps
  • Symmetric arithmetic rounding
  • Output saturation or wrap modes
  • FPGA sample rates up to 600 MHz
  • Matlab®, FDAtool® and Simulink® compatible

Benefits

  • Technology independent soft IP Core
  • Suitable for FPGA, SoC and ASIC
  • Supplied as human-readable source code
  • One-time license fee with unlimited use
  • Field tested and market proven
  • Any custom modification on request

Block Diagram

Ultra-speed FIR Filter Block Diagram

Deliverables

  • VHDL source-code (or Verilog on request)
  • Simulation test bench
  • Examples and scripts
  • Full pdf datasheet
  • One-to-one technical support
  • One years warranty and maintenance

Technical Specifications

Foundry, Node
All
Availability
Immediate
×
Semiconductor IP