Ultra-low power 32-bit processor resistant to physical damage

Overview

Key Features

• Instruction set: T-Head ISA (32-bit/16-bit variable-length instruction set);
• Pipeline: 2-stage;
• General register: 16 32-bit GPRs;
• Bus interface: Dual bus (instruction bus + data bus);
• Memory protection: 0 to 8 optional protection zones;
• Tight coupling IP: Interrupt controller and timer;
• Multiplier: Optional slow multiplier and fast multipliers;
• Anti-physical attack engine: Effectively protecting various invasive and non-invasive physical attacks;
• Secure execution technology: Resists any hardware and software attacks, and increases system security;
• Low-power cache: Reduces system memory access latency, and improves memory efficiency;
• Interrupt response acceleration technology: Enhances the system's real-time performance to allow users to quickly enter the corresponding service program;
• Control of average power consumption and peak power consumption: Adaptive to specific application scenarios with stringent requirements for power consumption;
• Products equipped with S802 have successfully passed various financial security certifications: EAL4+ Security Certification; BCTC Security Certification; National Certificate in Security (Level 2); FIPS Security Certification.

Block Diagram

Applications

• Wireless Connectivity;
• Industrial Control;
• IoT Security.

Technical Specifications