Having the lowest network latency is critical for Accelerated Finance. To achieve the lowest Ethernet latency, it is necessary to optimize the layer-1 PHY and the layer-2 MAC. Algo-Logic Systems’ Ultra-Low-Latency (ULL) PHY+MAC minimizes roundtrip latency by several hundred nanoseconds as compared to vendor supplied IP cores. Algo-Logic Systems’ ULL PHY+MAC design implements 10GBASE-R MAC and PCS (Physical Coding Sub-layer) functionality in an FPGA by using logic optimized for latency.
The ULL PHY+MAC is compatible with multiple FPGA platforms that support SERDES rates of 10.3125 Gbps while bypassing all PCS and excessive buffering features. The MAC interfaces to user logic via the 64-bit Avalon-ST bus or AXI4-Stream standards.
In this fashion, Algo-Logic Systems’ ULL PHY+MAC is designed to seamlessly replace much slower default PHY+MAC implementations that come with standard FPGA platforms.
Ultra-Low-Latency 10GE PHY+MAC
Overview
Key Features
- 89ns round-trip (fiber-to-fiber or gate-to-gate) for 10 Gigabit Ethernet, first-bit to first-bit
- Reconciliation sub-layer implementation compliant with IEEE802.3
- Local fault and remote fault detection and handling
- Frame Check Sequence (FCS) insertion and verification at line rate
- Automatic transmit padding, jumbo frame support, transmit and receive statistics counters
- Compatible with multiple FPGA platforms as soft-logic around SERDES
- Supports both standard Avalon-ST/ AXI4-Streambus interfaces
- Direct replacement for high-latency default vendor cores
- High level architecture Ethernet MAC design is flexible in its use of system clock (on the Avalon ST side)
- Low gate count(1,271 ALMs on Stratix V)
- Includes support for 1Gbps Ethernet
Block Diagram
Technical Specifications
TSMC
Pre-Silicon:
40nm
LP