InCirT’s APLL12GGF22 is the ring-oscillator based analogue-PLL which provides ultra-low jitter (600fs rms jitter at 12.5GHz) and low-power consumption (5.3mW at 12.5GHz) operating from 6GHz up to 12.5GHz.
Due to its ultra-small area (0.007sq mm) APPLL12GGF22 is an ideal candidate for SOC designs requiring multiple clock domains.
APLL12GGF22 is an integer-N PLL which gives flexibility to the designers to find the best clock-domain in the overall system.
Ultra-low jitter, low-power ring-oscillator-based PLL - 6GHz-12.5GHz
Overview
Key Features
- Ultra-low jitter feature which makes PLL suitable for variety of applications such as ADC, DAC and high-speed interface, TRx systems.
- Highly compact and small area (0.007sq mm) benefiting ring-oscillator architecture.
- The generated output frequency can vary from 6GHz to 12.5GHz with input frequency of 50MHz.
- Programmable integer divider.
- 8 multi-phase clocks are obtained simultaneously.
- Two supply domains are required for analogue PLL.
Benefits
- Ultra-low jitter (less than 600fs rms jitter)
- Low power (Less than 5.3mW)
- Wide tuning range (from 6GHz to 12.5GHz)
- Ultra-small area (0.007sq mm)
- Integer-N multiplication with reference frequency of 50MHz
- Highly compact and easy integration
Applications
- SoCs requiring multiple-clock domains
- ADC and DAC
- High-speed SerDes
Deliverables
- GDSII layout
- Integration support
- DRC, LVS reports
- Datasheet including characterization results
- CDL netlist for LVS
- Verification report
Technical Specifications
Foundry, Node
GlobalFoundries 22FDX
Maturity
Silicon Proven
Availability
Now Available
Related IPs
- Ultra-low jitter, low-power ring-oscillator-based PLL-4.5GHz-9.5GHz
- Ultra-low Jitter Fractional-N Frequency Synthesizer PLL (5nm - 180nm)
- 4-GHz Jitter-optimized low-power digital PLL
- 1.5-GHz Jitter-optimized low-power digital PLL
- 4-GHz Jitter-optimized low-power digital PLL
- Low Jitter 1.25GHz to 2.5GHz Quadrature Output PLL