The Jitter Cleaning PLL macro is implemented in Analog Bits’ proprietary architecture that uses 0.9V core and 1.8V IO oxide devices. The PLL macro uses two clean externally filtered analog supply voltages at 0.9V and 1.8V, and up to 3 extra pads and additional on-package capacitors. The output clock is set to multiply by 8, (FOUT = FREF x 8). PLL divider ratios are to be set appropriately based on value of FREF to keep FVCO ≈ 14GHz. This is to limit the operating range of the VCO and to allow fine-tuning the VCO for best jitter/phase-noise performance (please see section “PLL Divider Settings”). The PLL is self-calibrated by the de-assertion of PLL_RESETB.
The relationships between the different frequencies of the PLL are as follows: FOUT = FREF x 8 FVCO = FREF x 8 x DDIVO2 x 4 In order to minimize noise coupling and maximize ease of use, the PLL incorporates a proprietary ESD structure, which is proven in several generations of processes. The PLL macro is designed for implementation in a flip-chip package.