TSMC embedded flash controller

Overview

The eSi-TSMC-Flash IP core provides an AMBA 3 AHB-lite interface to TSMC's embedded flash macros.

This AHB controller allows a CPU and other peripherals to easily read, execute code from, erase and program a TSMC embedded flash's data and information blocks.

Key Features

  • Supports access to one data memory and one information memory.
  • Optionally supports redundancy.
  • Optional ECC support with SECDEC (single-bit error correction, double-bit error detection).
  • Programmable read/write timings, to support different clock frequencies.
  • Write protection.
  • Discharge on brown out.
  • Triple AMBA 3 AHB-lite slave interfaces.

Deliverables

  • Verilog RTL
  • Testbench
  • Simulation and synthesis scripts
  • Documentation
  • C API

Technical Specifications

Foundry, Node
TSMC
Maturity
Silicon proven in multiple products
Availability
Immediate
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Semiconductor IP