This datasheet describes the HBM (High Bandwidth Memory) PHY IP, which could be integrated with HBM memory controller to provide HBM functionality. The HBM PHY is compliant to the JEDEC HBM2E & HBM2 standard. In 7nm, it supports data rates up to 3200 Mbps per data pin at DFI 1:2 mode. A DFI interface is provided by this HBM PHY IP to connect to HBM memory controller IP. Power information is described at subsection 3.2.1 in detail . Complete signal and power integrity analysis are verified on the GUC design flow to make sure all signal and power requirements are met.
HBM PHY IP includes one hard macro and one RTL module. The hard macro called as IGAHBMX02A is HBM Hard PHY includes command address module, data module, IO pads, PLL and DLL components required for HBM PHY function. The RTL module called as MLB (miscellaneous logic block) is provided to work with HBM Hard PHY. MLB RTL module includes functions such as training logic, JTAG controller interface for PHY DFT registers and BIST(Built-In Self Test) logic. HBM PHY evaluation mode is provided through MLB RTL module without the help of controller to complete the training sequences such as read data EYE training and write data EYE training which are required to guarantee HBM PHY IP functions. MLB training procedure is default enable in initial sequence to set HBM PHY by hardware as described in subsection 3.4.3. This MLB RTL module shall be integrated in SOC by users to work with HBM Hard PHY correctly.