IGAAFEV04A is a 500 MHz analog front-end circuit. IGAAFEV04A contains four 12 bit 250 MHz SAR 2-channel ADCs, four 12 bit 500 MHz Current Steering 3-channel DACs and one 500 MHz General-Purpose PLL. IGAAFEV04A support I2C, JTAG, and APB 3-in-1 interface to handle configuration and functionality control for ADC, DAC, and PLL. Individual power-down mode of each ADC, DAC, and PLL is built in for power consumption reduction.
IGAAFEV04A is designed and fabricated in TSMC 12 nm FF CMOS process.
TSMC CLN12FFC 500MHz Analog Front-End
Overview
Key Features
- TSMC 12 nm 0.8 V/1.8 V CMOS LOGIC FinFET Compact Process
- Metal scheme: 1P9M (2Xa1Xd_h_3Xe_vhv_2Z) + UT-ALRDL
- Operating junction temperature: -40 °C ~ 125 °C
- 2-ch 12 bit 250 MHz SAR ADC
- 3-ch 12 bit 500 MHz Current Steering DAC
- 500 MHz general-purpose PLL
- SoC interface data rate: 500 MHz
- Built-in pattern generator for DAC testing
- Built-in SRAM, and down sample for ADC test
- EHOST : APB, I2C, and JTAG register interface
- 1.8 V/0.9 V analog supply voltage and 0.8 V digital supply voltage
- Build in individual power-down mode for each ADC, DAC, and PLL
- Special layer and device type: DNW, High-R Resistor, ulvt, MOM cap, SRAM
- IP GDS size: 960 um (Width) x 4600 um (Height)
Technical Specifications
Foundry, Node
TSMC 12nm CLN12FFC
Maturity
Silicon proven
TSMC
Silicon Proven:
12nm