TSMC 65LP Combo IO with 2Gb/s LVDS and CMOS GPIO

Overview

Key Features

• TSMC 65 LP
• 2.5V/1.2V IO/Core transistors
• Fully compliant with TIA/EIA-644-A-2001
• Built-in, low parasitic ESD protection
• Easily integrates with TSMC I/O library cells
• All-in-ring® topology, so no core silicon area is used by LVDS
• The same cells operate with 2.5V/1.2V or 1.8V/1.2V power supplies
• Adjustable output common mode voltage (LVDS or SubLVDS mode)
• Adjustable driving current for buses with single or double termination
• Adjustable output driving current for CMOS GPIOs
• Standby/power down mode
• Internal bias voltage generation and bias current distribution circuitry
• Selectable on-chip termination resistor, with optional user tuning
• Digital loopback functions to ease ATE testing
• Up to 2 Gbps data rate LVDS

Applications

• Multi-purpose reconfigurable IO
• Point-to-point, point-to-multipoint or bus-based IC high-speed data communications
• Intra-package (e.g. MCM or SIP) inter-die high-speed data communications
• Backplane high-speed data communications
• High-speed serial communications (HDMI, SATA, PCIeX, etc.)
• Communication to LCD/OLED screens
• Video sensor digital data interface

Deliverables

• GDS II layouts
• LEF abstracts
• CDL netlists
• Liberty timings
• Verilog description
• A full datasheet
• An integration note

Technical Specifications