True Random Number Generator

Overview

Key Features

• Patented test circuits on the oscillators to detect lockingto periodic signals.
• Repeating output data detection on NRBG and DRBG (compliant with [FIPS 140-2]).
• Hardware implemented ‘Repetition Count’ and ‘Adaptive Proportion’ tests on the Noise Source (compliant with [SP 800-90B]).
• Continuous tests on the Noise Source (compliant with [AIS-31]): ‘monobit test’, ‘poker test’, ‘runs test’, ‘longruns test’ and ‘Noise Source failure’.
• Secure random data buffer wipe-after-read and zeroize functions (compliant with [FIPS 140-2]).
• Secure reading mode where data is only available on request, for a (configurable) limited time.
• Automatic shutdown on fatal errors.
• Automatic de-tuning of FROs after lock detection.
• Various on-line and off-line integrity and known answer tests on the Conditioning Function, DRBG andself-test circuits.
• Configurations available with countermeasures against Fault Injection Attacks.

Benefits

• True Random Number Generator
• Silicon-proven implementation
• Fast and easy to integrate into SoCs
• Flexible layered design
• Complete range of configurations
• World-class technical support

Block Diagram

Applications

• Security
• Cryptography
• Key generation
• Random number generation

Deliverables

• Documentation
  • Hardware Reference and Programmer Manual
  • Integration Manual
  • Noise & Entropy document
• Synthesizable Verilog RTL source code
• Self-checking RTL test bench, including test vectors and expected result vectors
• Simulation scripts
• Many different configurations possible:
  • Conditioning Function support
  • Fault Injection protected support
  • (optional) Deterministic Random Bit Generator
  • (optional) DMA handshake
  • Gate count ranging from: 10.9k + 11.5k to 56k + 11.5k gates
  • Up to 1 GHz

Technical Specifications