Tiny Hash IP core

Overview

The Helion Tiny Hash Core family for ASIC offers a combination of high functionality and low resource usage for lower data rate applications. The core is available in versions which support any combination of the secure hashing algorithms described in the Secure Hash Standard, FIPS PUB 180-3; namely SHA-1, SHA-224, SHA-256, SHA-384 and SHA-512. It can also support the standard Hash-based Message Authentication Code (HMAC) algorithm described in FIPS PUB 198-1 which is widely used for data authentication and integrity checking in a number of common data security protocols.

As standard the core supports up to four concurrent hash calculations (or two HMAC calculations), and offers full core state unload and reload to greatly improve system throughput when processing interleaved or packet-based data streams. Simple synchronous interfaces ensure easy system integration whether employed as a hashing accelerator for an embedded processor, or connected directly into a datapath.

Key Features

  • Implements one or more of SHA-1, SHA-224, SHA-256, SHA-384 & SHA-512 secure hash algorithms defined in FIPS PUB 180-3
  • Supports Keyed Hashing for Message Authentication (HMAC) to FIPS 198-1
  • Performs full message padding according to FIPS PUB 180-3
  • Provides high functionality for low resource, low data rate applications
  • Runs up to four concurrent hashes each using different hash algorithms
  • Supports full state unload/reload to optimise hashing of interleaved data
  • All state stored in small single-ported RAM or Register file for efficiency

Block Diagram

Tiny Hash IP core Block Diagram

Deliverables

  • Fully synthesisable RTL source code
  • VHDL/Verilog testbench with test vectors
  • User documentation

Technical Specifications

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Semiconductor IP