The Tessent Embedded Analytics Status Monitor provides visibility and monitoring of any circuitry within a System-on-Chip (SoC). It affords many of the benefits of a logic analyzer, but with no need to bring signals off-chip.
The Status Monitor provides a wide variety of functions including debugging, reporting diagnostics, and performance profiling. It can be parameterized at instantiation to precisely monitor the logic signals within the host SoC that interest the engineering team, giving visibility of those internal signal lines that would otherwise be inaccessible once the SoC is delivered, as well as during FPGA prototyping or emulation.
All Tessent Embedded Analytics monitors (IPs), can be accessed via a dedicated, secure communication infrastructure. Non-intrusive debug and monitoring using an off-chip host or debugger is facilitated through USB 2, USB 3, JTAG, or Aurora interfaces. Embedded software can drive the system via an AXI interface to create a self-contained on-chip monitoring system.
Tessent Status Monitor
Overview
Key Features
- Analyzes on-chip signals and interfaces.
- Measure the performance and verify the functionality
- “Logic-analyzer” type visibility of internal signals not normally detectible off-chip
- Run-time configurable
- Use to interact with other Tessent Embedded Analytic modules for complex triggering scenarios
Benefits
- Accelerate SoC debug and SW development
- Identify and resolve hard-to-identify bugs significantly faster compared to traditional software-only solutions
- Root-cause performance degradations and memory corruption
- Better visibility and analytics
- Integrated part of the Tessent Embedded Analytics whole system solution
Block Diagram
Deliverables
- Parameterized soft core (Verilog RTL)
- Available UVM verification IP
- Optional Tessent SystemInsight IDE software
- Optional Tessent Embedded SDK software development kit
Technical Specifications
Maturity
In silicon
Availability
Now