Sub-Nanosecond Resolution, Sub-Microsecond Accurate, FPGA System Timer Component
Overview
Atomic Rules TimeServo is a RTL IP core that serves the function of an FPGA’s System Timer or Clock. Although specifically designed to support the needs of line-rate independent packet timestamping, TimeServo may find use where there is the need for a high-resolution, modest-accuracy timebase. TimeServo’s PI-DPLL allows a local TCXO to be disciplined by an external 1 PPS signal to achieve excellent syntonicity. In conjunction with timestamp-capable MACs (not included) and host-control software (as-is examples provided), TimeServo is a vital and central component of an IEEE-1588/PTP system.
Key Features
- Flexible and independent clocks for control-plane and reference clock
- Up to 32 outputs, each in their own clock domain
- Outputs individually runtime switchable between three 80-bit formats (Binary 48.32, IEEE Ordinary, IEEE Transparent)
- Software control and observability from AXI control plane
- Internal logical 120-bit resolution phase accumulator
- Proportional/Integral controlled Digital Phase Locked Loop (PI-DPLL)
- Observable output of digital Phase-Frequency Detector (PFD Monitor)
Benefits
- Single-component solution for providing coherent time within an FPGA
- Operates with or without an externally provided Pulse-Per-Second (PPS) Reference
- Sub-Nanosecond Resolution, Sub-Microsecond Accurate, FPGA System Timer Component
Block Diagram
Deliverables
- “As is” software control utility to set/get common settings as well as observe behavior.
- “As is” example design using Atomic Rules Arkville (Arkville NOT included) showing application with IEEE-1588 Precision Time Protocol (PTP). (To be included in 17.11 release.)