SSTL_15_18 IO Pad Set
Overview
The SSTL_15/18 pad set is a full complement of I/O, calibration, power, and spacer cells that are necessary to assemble a padring by abutment. Since the SSTL_15/18 normally operates with its own isolated power domain (1.5V/1.8V), a “rail-splitter” support cell (SPP_RS_005_15V) is included to allow the designer to easily break the lines that should not connect to the rest of the padring, while allowing VDD and VSS to be continuous within the padring.
Key Features
- Full DDR3 capability - 800MHz (1600 Mbps)
- Full DDR2 capability
- Low Power driving standard DDR3 memories
- 2.5V FETs
- Full complement of cells to build padring (20)
- Full ODT Capability - dynamic 6-Bit PVT calibration (external reference resistor)
Deliverables
- Physical abstract in LEF format (.lef)
- Timing models in Synopsys Liberty formats (.lib and .db)
- Calibre compatible LVS netlist in CDL format (.cdl)
- GDSII stream (.gds)
- Behavioral Verilog (.v)
- Layout Parasitic Extraction (LPE) SPICE netlist (.spice)
- Databook (.pdf)
- Library User Guide - ESD Guidelines (.pdf)
Technical Specifications
Foundry, Node
GLOBALFOUNDRIES, 40nm
Maturity
Silicon Proven
Availability
Available Now
GLOBALFOUNDRIES
Silicon Proven:
40nm
LP