The Veriest SPI to AMBA AHB Master Bridge Design IP offers a simple solution to provide "backdoor" access from external SPI master devices to the embedded AMBA AHB bus. The SPI to AMBA AHB Bridge utilizes a simple but effective protocol for reads and writes over the chip-embedded AMBA AHB. The SPI transactions are protected in both directions by a CRC checksum field The external SPI device can be a CPU such as a Tegra, OMAP or other similar device. Driver development for such devices to support the Veriest SPI to AMBA AHB Bridge is very simple.
SPI to AMBA AHB Master Bridge
Overview
Key Features
- Serial SPI Compatible
- Low Pin Count Interface (4 pins)
- Can be shared with other chip I/O functions
- AMBA AHB 3.0 Compatible
- Compatible with NVIDIA Tegra devices
- Compatible with Texas Instruments OMAP devices
- Simple SPI Protocol supporting Reads and Writes
- CRC protection in both directions
- Transfer Acknowledge and Error Detection
- Security Features can be added upon request
Benefits
- Low Gate Count
- Low Power Consumption
- Fully Verified
- Spyglass Lint Validated
- Standards Compliant
Block Diagram
Applications
- General System on Chip Use
Deliverables
- Synthesizable Verilog RTL
- Verilog test bench and test cases
- Detailed block diagram and technical documents
Technical Specifications
Maturity
Fully Verified
Availability
Now