SPI (Serial Peripheral Interface) Flash Verification IP

Overview

SPI (Serial Peripheral Interface) Flash is the serial synchronous communication protocol developed by SPI Block Guide V04.01. SPI Flash VIP can be used to verify Master or Slave device following the SPI Flash basic protocol as defined in Motorola's M68HC11 user manual rev 5.0. It can work with Verilog HDL environment and works with all Verilog simulators that are support SystemVerilog.

SPI (Serial Peripheral Interface) Flash Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

SPI (Serial Peripheral Interface) Flash Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

Fully compatible with SPI Flash standards.
Supports SQI interface specification and common flash device models.
Follows Serial Flash specification as defined in WINBOND, MICRONIC, MACRONIX, MICRON, SPANSION, Silicon Storage technology (SST) and many more.
Supports single, dual and quad mode bus width operation.
Supports spansion DDR Flash model.
Supports Master and Slave Mode.
Supports bus width 1 bit and 4 bit.
Supports baud rate selection.
Supports clock polarity (CPOL) and clock phase (CPHA) selection.
Supports single and burst transfer mode. Supports on the fly generation of data.
Supports Glitch insertion and detection .
Supports customized single/dual/quad modes for Command, Address and Data phase.
Supports configurable dummy cycles.
Supports configurable memory density.
Supports software and hardware write-protect.
Supports discoverable parameters (SFDP) register.
Supports volatile & non-volatile Status Register Bits.
Supports software and hardware Reset.
Supports backdoor access for memory and registers.
Supports quad peripheral interface (QPI) reduces instruction overhead.
Support allows true XIP (execute in place) operation.
Supports advanced security features.
Supports program 1 to 256 byte per programmable page.
Supports erase/program suspend & resume.
Supports flexible erase operation like,

4KByte sector erase
32KByte block erase
64KByte block erase

Detects and reports Mode Fault error.
Built in functional coverage analysis.
Supports Callbacks in master, slave and monitor for modifying, and sampling data/cmd on SPI Flash bus.
Master contains rich set of commands.
Notifies the test bench of significant events such as transactions, warnings, and protocol violations. This can be written to separate log files.
SPI Flash Verification IP comes with complete test suite to test every feature of SPI Flash specification.

Benefits

Faster testbench development and more complete verification of SPI Flash designs.
Easy to use command interface simplifies testbench control and configuration of slave and master.
Simplifies results analysis.
Runs in every major simulation environment.

Block Diagram

Deliverables

Complete regression suite containing all the SPI Flash testcases.
Examples showing how to connect various components, and usage of Master, Slave and Monitor.
Detailed documentation of all class, task and function's used in verification env.
Documentation contains User's Guide and Release notes.

Technical Specifications

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