SPI/BOSCH Verification IP

Overview

SPI/BOSCH Verification IP provides an smart way to verify the serial synchronous communication protocol.The SmartDV's SPI/BOSCH Verification IP is fully compliant with SPI Block Guide V04.01 of Bosch SMB380 Triaxial acceleration sensor Specification and provides the following features. It can work with Verilog HDL environment and works with all Verilog simulators that are support SystemVerilog.

SPI/BOSCH Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

SPI/BOSCH Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

Follows SERIAL_FLASH basic specification as defined in Bosch SMB380 Triaxial acceleration sensor
Support Master and Slave Mode
Supports data width of 8 bit
Supports 3-wire,4-wire interface
Support baud rate selection
Support internal clock division check.
Support clock polarity and clock phase selections.
Support single and burst transfer mode.
Support Write and Read middle abort
Support on the fly generation of data.
Supports constraints Randomization.
Glitch insertion and detection
Built in functional coverage analysis.
Supports backdoor initialization of data.
Status counters for various events on bus.
Supports single,dual bus width operation
Supports Callbacks in master, slave and monitor for modifying, and sampling data/cmd on Bosch.
Bosch Slave can be configured as standard device or can use FIFO for data passing.
Master contains rich set of commands for both standard device and FIFO model mode.

Benefits

Faster testbench development and more complete verification of Bosch designs.
Easy to use command interface simplifies testbench control and configuration of slave and master.
Simplifies results analysis.
Runs in every major simulation environment.

Block Diagram

Deliverables

Complete regression suite containing all the SPI/BOSCH testcases.
Examples showing how to connect various components, and usage of Master, Slave and Monitor.
Detailed documentation of all class, task and function's used in verification env.
Documentation contains User's Guide and Release notes.

Technical Specifications

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