SPI 4.2 MACO Core

Overview

Key Features

• Fully compliant with OIF-SPI4.02.0 Specification
• Supports up to 256 logical ports
• 700 Mbps operation in Static Mode
• 1+ Gbps operation in Dynamic Mode
• Transmit/Receive Data Path
• 16 bits wide, in-band port address, SOP, EOP indication, error control
• LVDS I/O (IEEE 1596.3 – 1966 [1], ANSI/TIA/EIA-644-1995[2]
• Source synchronous double edge clocking at 311MHz minimum
• Static and Dynamic Alignment Modes
• Up to 1 Gbps Dynamic Phase Alignment
• Up to 700 MHz Static Alignment
• Additional Quarter Rate Mode for sub 10G traffic
• Transmit/Receive FIFO Status
• 2 bit parallel FIFO status indication, in-band Start of FIFO status
• LVTTL I/O or optional LVDS I/O (IEEE 1596.3)
• Source synchronous clocking
• Various run-time user controls:
• Individual receiver/transmitter resets
• De-skew only reset, AIL only reset
• Force idles (transmitter)
• Enable/Disable Packing (transmitter)
• Training Pattern (CAL_M, MAX_T) Programmable burst modes to support NPU requirements
• Link Layer Buffer Management Options (NEW):
• Shared or per-channel buffer manager
• Up to 16 separate physical FIFOs per Tx/Rx direction
• Transmit Bandwidth Manager and Receive Channel Mapper
• Parameterizable packet overflow and packet error drop
• Graceful packet overflow drop
• Both store & forward as well as cut-through operation
• Parameterizable independent buffer depth per transmit and receive direction
• Per channel empty, almost empty, full and almost full status
• Programmable almost empty and almost full thresholds per channel
• Dynamic channel provisioning
• Programmable sequencer based scheduler.
• Supported by System Bus and Serial Memory Interface (SMI) for in-circuit controllability
• Pre-engineered hard cores using MACO technology to conserve power, FPGA resources and designer time
• Multiple SPI4 IP core support per device
• Supported in Windows, Linux, or Unix based tool flows
• Supports both Verilog and VHDL tool flows

Block Diagram

Technical Specifications