SPDIF-Rx-Pro : Configurable SPDIF-AES/EBU Receiver

Overview

Key Features

• Supports the IEC60958 (SPDIF), AES3 standards for PCM audio transmission
• Supports the IEC61937, SMPTE 337M standards for non-PCM (ie, compressed) audio transmission
• Uses a single domain clock frequency, unrelated to the sample frequency
• Supports up to 24 bits per sample
• Outputs recovered sample bit clock of frequency 64xFs
• Separate interfaces for data and control
• Supports any sample rates as long as the system clock frequency equals or is greater than 540*FS, including 32, 44.1, 48, 96 and 192 kHz
• Audio data FIFO of configurable size, reporting the number of samples in FIFO and with programmable almost full condition
• Lock time less than 3 sub-frames
• Channel Status and User Data memory mapped buffers with programmable masks for change notification

Benefits

• Modular Structure using optional Add-on-Modules (AOM)
• Permits rapid implementation of a configurable audio receiver for SPDIF and all its variations
• Purely digital solution: avoids the use of an analog PLL for frequency locking
• Reduced bandwidth by automatic removal of stuffing bits in non-PCM mode
• Flexible backend interface: AMBA®, CoreConnect™ or just parallel with REQ/ACK handshaking

Deliverables

• Verilog source code or FPGA netlist
• Verilog testbench for RTL simulation
• Synthesis constraints
• Datasheet
• Example software driver

Technical Specifications