SpaceFibre Verification IP

Overview

The SpaceFibre Verification IP is compliant with ECSS Draft F3 specification and verifies SpaceFibre interfaces. It includes an extensive test suite covering most of the possible scenarios. It performs all possible protocol tests in a directed or a highly randomized fashion which adds the possibility to create the widest range of scenarios to verify the DUT effectively.

SpaceFibre Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

SpaceFibre Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

Compliant with SpaceFibre ECSS Draft F3 Specification.
Supports data rate up to 2 Gb/s.
Multilaning improves the data rate up to 20 Gb/s.
Supports full duplex point to point serial data communication links.
Supports the following interfaces

Virtual Channel Interface
Broadcast Channel Interface

Supports broadcast messaging services.
Supports the following layers.

Network layer
Quality layer
Multi-lane layer
Lane layer
Physical layer
Management layer

Supports retry capability when frame is missing or having error.
Supports the following control words.

Lane control words
Lane synchronization control words
Retry control words
Framing control words
Flow control words
Receiver error detection control words

Supports the following frame types.

Data frame
Broadcast frame
Idle frame

Supports link error recovery.
Supports Scrambler & Descrambler.
Supports 8b / 10b encoding.
Supports 16 bit CRC.
Supports 7 bit sequence numbering.
Supports serialization and deserialization of 10 bits, 20 bits or 40 bits wide.
Supports the injection and detection of following errors.

Disparity error
Symbol error
Invalid code error
Invalid address error
FCT credit counter overflow error
Sequence error
Frame error
Input buffer overflow error
Link error

Glitch insertion and detection.
Monitors, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
Supports constraints Randomization.
Status counters for various events on bus.
Callbacks in Master, Slave and Monitor for user processing of data.
SpaceFibre Verification IP comes with complete compliance test suite to test every feature of SpaceFibre specifications.
Functional coverage for complete SpaceFibre features.

Benefits

Faster testbench development and more complete verification of SpaceFibre designs.
Easy to use command interface simplifies testbench control and configuration of Master and Slave.
Simplifies results analysis.
Runs in every major simulation environment.

Block Diagram

Deliverables

Complete regression suite containing all the SpaceFibre testcases.
Examples showing how to connect various components, and usage of Master, Slave and Monitor.
Detailed documentation of all class, task and function's used in verification env.
Documentation also contains User's Guide and Release notes.

Technical Specifications

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