The SpaceFibre IP core supports up to 8 lanes. On the Microchip SmartFusion2 the bit rate is the maximum allowed by the device, 2Gpbs per lane (16 Gbps). In the case of the Xilinx Zynq UltraScale+ this rate is 8Gbps per lane (64Gbps total). This IP core comes in 3 different versions. The first one is presented to the processor as a peripheral (AXI/AHB), the second one is a "bare metal" implementation that can be connected to any HDL design without any processor involved or maximum bitrate is needed. The last one is a bus extensor MMAP custom implementation on top of SpaceFibre. For the peripheral flavor, Linux support is available for transmitting raw frames or present it to the OS as a networking interface, supporting TCP/IP.
SPECIFICATIONS
| End of packet | Yes |
| Virtual channels | No |
| Multilane | 1 to 8 |
| Bitrate | 2 Gbps (SF2) 8 Gbps (ZynqMP) |
| Packet retransmission on error | Optional |