Innovative architecture to meet the SDH/ Sonet Jitter Spec utilizing deep sub-micron single poly CMOS process
Fully in compliance with ANSI, Bellcore and ITU jitter Specifications
Proven in multi-port end customer SOC designs
Designed for multi- port applications using re-usable building blocks targeted for process migration/ new application domains
Innovative (patent pending) CMOS architecture to guarantee compliance with Bellcore and ITU-T specifications for jitter tolerance, jitter transfer, and jitter generation
Proprietary Advanced Signal Processing techniques utilized for clock recovery provides on-chip filtering : immunity to external/PCB noise problem in existing solutions
Designed for multiple integration on a single IC for System-On-Chip applications
Custom configurable width serializer-deserializer (SERDES) option
SONET/SDH OC-3 / OC-12 Transceiver/CDR PHY
Overview
Key Features
- Fully integrated transceiver architectures that include: Clock synthesis, Clock Recovery, Wave shaping, low-jitter LVPECL interface, S/P/S functions.
- High frequency PLLs with integrated on chip loop filters.
- Supports 155.52 Mb/s (OC-3), 622.08 Mb/s (OC-12) with Selectable reference frequencies of 77.76 or 155.52 MHz.
- LVPECL or LVDS circuitry for external interfacing to optical units.
Deliverables
- GDS II stream file.
- Application Documentation.
Technical Specifications
Maturity
Silicon Proven
Availability
Now