CEI-6G-SR PHY

Overview

Key Features

• Receiver equalization for enhanced jitter tolerance
• Receiver jitter tolerance at 3.125 Gbps is >20% improvement over XAUI specification
• Programmable TX levels with multiple pre-cursor and post-cursor emphasis options
• Automatic driver/receiver impedance calibration
• 8/10 bit interface or 16/20 bit interface
• Signal detection
• Power saving modes
• Status pins for checking PHY functionality
• Integrated bandgap
• Extensive built in testability
• At-speed BIST circuitry with various PRBS and 8B10B patterns
• Multiplexed scan for testability of all digital logic
• Eye width mapping and on chip jitter generation capability
• Loop back modes
• Serial Control Register
• Support for DC and AC JTAG (AC EXTEST)

Benefits

• Low Risk - Silicon proven today in multiple foundries and processes with Extensive Si characterization data
• Excellent Interoperability - LC tank oscillator that gives low noise and jitter
• Superior Noise Immunity - Fully differential circuitry and Voltage Regulator for enhanced noise immunity
• Low Power - As low as 60mW per lane at 3.125Gb/s
• Minimal Area - for Wire bond as well as flip-chip package
• Improve Test Coverage - Multiple loopback modes with 12 built-in patterns
• Scan built in to all digital,Serial Control Register (SCR) for simplified testing, JTAG support (DC and AC )
• Lowest Total Cost of Ownership
• Customization/ Integration support

Block Diagram

Applications

• High-speed Interconnects
• Backplanes
• Optical Modules

Deliverables

• Abstract - LEF
• Behavioral Model -Verilog
• Timing Model -.lib
• High-speed IO Model - hSpice
• LVS Netlist - cdl
• Physical database - GDSII
• Documentation - pdf

Technical Specifications