SMPTE SDI Transmitter IIP

Overview

Key Features

• Compliant with standard protocol of SMPTE SDI 2.2A
• Full SMPTE SDI Transmitter device functionality
• Supports 12 Gb/s Signal/Data Serial Interface as per SMPTE ST 2082-1:2015
• Supports 6 Gb/s Signal/Data Serial Interface as per SMPTE ST 2081-1-2015
• Supports Source Image Format and Ancillary Data Mapping for the 3 Gb/s Serial Interface as per SMPTE ST 425-1:2011
• Supports 1.5 Gb/s Signal/Data Serial Interface as per SMPTE ST 292-1:2011
• Supports Dual Link 1.5 Gb/s Digital Interface for 1920 x 1080 and 2048 x 1080 Picture Formats as per SMPTE ST 372:2011
• Supports 1280 x 720 Progressive Image Sample Structure Analog and Digital Representation and Analog Interface as per SMPTE 296M-2001
• Supports 1920 x 1080 Image Sample Structure, Digital Representation and Digital Timing Reference Sequences for Multiple Picture Rates as per SMPTE 274M-2008
• Supports D-Cinema Distribution Master - Image Pixel Structure Level 3 - Serial Digital Interface Signal Formatting as per SMPTE 428-9-2008
• Supports 2048 x 1080 Digital Cinematography Production Image FS/709 Formatting for Serial Digital Interface as per SMPTE ST 2048-2:2011
• Supports 2048 x 1080 and 4096 x 2160 Digital Cinematography Production Image Formats FS/709 as per SMPTE ST 2048-1:2011
• Supports Ultra High Definition Television - Image Parameter Values for Program Production as per SMPTE ST 2036-1:2014
• Supports Ancillary Data Packet and Space Formatting as per SMPTE ST 291:2010
• Supports Dual standard support for 270-Mbps and 1.5-Gbps SDI
• Supports 10-bit/20-bit/40-bit parallel interfaces
• Supports Serialization and de-serialization
• Supports NRZI channel encoding
• Supports below video format mapping structures:
  • 4:4:4 (X'Y'Z')/12-bit
  • 4:4:4 (R'G'B')/10-bit
  • 4:4:4 (R'G'B')/12-bit
  • 4:4:4 (Y'C'BC'R)/10-bit
  • 4:2:2 (Y'C'BC'R)/10-bit
  • 4:2:0 (Y'C'BC'R)/10-bit
  • 4:4:4 (Y'C'BC'R)/12-bit
  • 4:2:2 (Y'C'BC'R)/12-bit
  • 4:2:0 (Y'C'BC'R)/12-bit
  • 4:4:4:4 (R'G'B'+A)/10-bit
  • 4:4:4:4 (Y'C'BC'R+A)/10-bit
• Supports up to Quad-link channel interface
• Supports 16-bit/20-bit/24-bit Digital Audio data
• Supports 4 to 32 Audio channels
• Supports 24-Bit Digital Audio Format for SMPTE 292 Bit-Serial Interface as per SMPTE ST 299-1:2009
• Supports Extension of the 24-Bit Digital Audio Format to 32 Channels for 3 Gb/s Bit-Serial Interfaces as per SMPTE ST 299-2:2010
• Supports Audio extended data packets
• Supports for Scrambler
• Supports insertion of scrambler errors
• Supports error correction code (ECC)
• Detects and reports the following errors:
  • Invalid EAV code
  • Invalid SAV code
  • Invalid CRC error
  • Invalid LN error
  • Invalid parity error
  • Invalid NRZI encoding error
  • Invalid 10bit code
  • ECC errors
  • Invalid ADF errors
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready
• Simple interface allows easy connection to microprocessor/microcontroller devices

Benefits

• Single Site license option is provided to companies designing in a single site.
• Multi Sites license option is provided to companies designing in multiple sites.
• Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
• Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

Block Diagram

Deliverables

• The SMPTE SDI Transmitter interface is available in Source and netlist products.
• The Source product is delivered in verilog.If needed, VHDL and SystemC can also be provided
• Easy to use Verilog Test Environment with Verilog Testcases
• Lint, CDC, Synthesis, Simulation Scripts with waiver files
• IP-XACT RDL generated address map
• Firmware code and linux driver package
• Documentation contains User's Guide and Release notes.

Technical Specifications